基于FPGA的图像数据缓存控制器设计

Image data cache controller design based on FPGA

介绍了SDRAM存储器的工作原理及其特点,给出了以大规模可编程逻辑器件FPGA为核心、SDRAM为缓存的高速图像数据缓存控制器的设计.该控制器实现了对SDRAM接口以及读写FIFO的时序控制,并通过在SDRAM存储器内部切换帧的方法大大提高了图像数据的传输效率.

This paper introduces the working principle and characteristics of SDRAM firstly. Then a image data controller design in the FPGA is presented. The controller achieves the SDRAM interface time-series and FIFO＇s reading and writing. Test results show that the controller through a frame switch method inside the SDRAM can improve the image data transmission efficiency greatly.