基于FPGA的1553B总线终端设计

Design of MIL-STD-1553B Terminal Based on FPGA

详细设计了基于FPGA的MIL-STD-1553B总线终端,采用了DSP(TMS320F2812)作为1553B总线终端的主处理器,FPGA(XC3S500E)作为1553B协议芯片,开展了总线耦合、时钟管理、DSP及FPGA交互等电路设计,并通过VHDL语言实现了1553B总线通讯功能;通过实验证证明该设计能够完成BM/RT两种模式的工作,能处理多种消息格式的传输,并具有较强的检错能力;通过实际工程使用,该终端实时性好,性能可靠,具有一定的应用推广价值。

This article researched the MIL--STD--1553B bus terminal based on the FPGA and designed it in details. In the designation the DSP （TMS320F2812） was adopted as the main processor of the 1553B bus terminal, the FPGA （XC3S500E） as the 1553B protocol chip. The research carried out the circuit designations of the bus coupling, timer management, DSP, FPGA interaction and so on, and accomplished the function olf the 1553B bus communication using the language of VHDL. The experiment shows that the design implement two kinds of terminal functions, and it can process a variety of message communications in multiple formats, and have great function of detect error. According to the actual project applying, the bus terminal was confirmed to have high real--timing, reliable performance and had certain application and promotion value.