一种分布控制双时钟FIFO的设计与实现

Design and implementation of a distributed-controlled dual-clock FIFO

双时钟FIFO是一种常用的跨时钟域数据交接电路。随着SoC芯片内部时钟域种类的增加,传统方式实现的双时钟FIFO会增加时钟网络设计的复杂度,这已经成为影响芯片规模扩大和频率提升的因素之一。提出了一种分布控制双时钟FIFO结构,运用源同步数据传输技术,避免了将发送方时钟树分布到接收方而增加时钟网络设计的复杂度。详细介绍了该结构的一种实现方法,并针对性能和可实现性,简要介绍了该设计可进一步采取的优化措施。

Dual-clock First-Input First-Out （FIFO） structure is very useful for transferring data between modules operating in different clock domains. As more and more independent clock domains are integrated onto a System-on-a-Chip （SoC）, the traditional dual-clock FIFO structure increases the design complexity of clock networks, thus blocking the increase of the chip size and the frequency. The paper proposed a distributed-controlled dual-clock FIFO structure. The proposal uses the technology of source-synchronous data transfer so as to avoid the design complexity of clock networks, which is induced by distributing the sender＇s clock into the receiver＇s clock domain. The paper implemented this design and further introduced its optimization according to the performance and the realizability.