14位100MSPS流水线ADC的低功耗设计

Low power design for 14-bit 100MSPS pipelined ADC

为实现14位100MSPS流水线模数转换器(ADC)的低功耗设计,提出了一种新型的运放和电容共享技术。该技术将流水线ADC的前端采样保持电路(SHC)并入第一流水线级,并在后面的流水线级中相邻两级使用运放共享技术,消除了常规的运放和电容共享技术所存在的需要额外置零状态和引入的额外开关影响运放建立时间的缺点。芯片采用TSMC 0.18μm互补型金属氧化物半导体(CMOS)混合信号工艺,仿真结果表明,在100MSPS采样率和10MHz输入信号频率下,ADC可达到77.6dB的信号噪声失调比(SNDR),87.3dB的无杂散动态范围(SFDR),±0.4LSB的微分非线性(DNL),±1LSB的积分非线性(INL),0.56pJ/conv的品质因数(FOM),在3.3V供电情况下功耗为350mW。

In order to implement low power design for 14-bit 100MSPS pipelined analog-to-digital converter（ADC）,a novel opamp and capacitor sharing technique is proposed.The ADC merges sample-and-hold circuit（SHC） and the first stage by proposed technique with the rest stages using opamp sharing technique.The proposed technique eliminates the disadvantages of the conventional opamp and capacitor sharing technique.The chip is designed in TSMC 0.18μm complementary metal-oxide-semiconductor（CMOS） mixed signal technology.Simulation results show that when the sample rate is 100MSPS and input signal frequency is 10MHz,the ADC achieves signal-to-noise and distortion ratio（SNDR） of 77.6dB,spurious free dynamic range（SFDR） of 87.3dB,differential nonlinearity（DNL） of ±0.4LSB,integral nonlinearity（INL） of ±1LSB,figure of merit（FOM） of 0.56pJ/conv,power of 350mW at 3.3V supply.