高速交换矩阵调度器的FPGA设计

FPGA Design for Scheduler of High-speed Switch Matrix

提出了一种并行迭代算法调度器的可编程逻辑门阵列(FPGA)的实现方法。调度器主要由仲裁器和有限状态机2部分组成,采用温度型可编程优先编码器的设计方法,大大降低了仲裁器输入输出的时延,提高了调度器的工作速度;同时,采用流水线设计进一步减少了每次调度需要的时钟周期数,有效地解决了输入端口和输出端口的阻塞。设计方法可以用于目前所有基于RR指针的三步迭代算法的设计。

The FPGA design of a scheduler based on parallel iterative algorithm is presented. The scheduler consists of arbiter and finite state machine. By adopting a programmable priority encoder,the time delay of the arbiter between the input and output ports is de- creased, and the operation rate of the scheduler is improved. Meantime, the number of clock cycles is reduced through a pipelined implementation. The design effectively resolves the blocking problem of the input and output ports,and is appropriate for all three-step itera- tive algorithms based on the cursor of RR.