摘要
针对遥测信号处理器的设计原理,增加少量硬件电路,利用其自身FPGA剩余逻辑资源完成自检模块设计,实现了信号处理器BIT测试功能,提高了信号处理器在挂机状态下的测试覆盖率和故障检测率。
The design principle of telemetry signal processor is introduced. tional hardware circuit and taking advantage of the rest logic resource in FPGA is rate and test coverage of telemetry signal processor hanging on the aerobat. BIT ized by designing self-checking module based on this method A method by introducing an addi- given to enhance the fault detection of telemetry signal processor is real-
出处
《电子科技》
2013年第6期31-33,36,共4页
Electronic Science and Technology
