面向延迟和面积平衡的时钟网变线宽算法

A WIRE SIZING ALGORITHM FOR DELAY AREA BALANCED CLOCK ROUTING

在深亚微米下 ,变线宽技术是互连线优化的一种有效方法 .针对时钟网布线 ,提出一种分布优化时延、面积和时钟偏差的变线宽算法 ,其中各阶段的优化是有机结合的 .首先 ,提出一种基于敏感度的方法优化互连线树的延迟 ;而后在满足延迟约束的条件下 ,通过近似规划法使连线面积的增加最小 ;最后 ,为了确保时钟偏差小于给定的约束 ,进一步对时钟树的树枝宽度进行局部调整 .实验表明 ,通过将基于敏感度的方法和较严格的数学规划方法结合起来可有效地处理时钟网延迟、面积和时钟偏差的平衡关系 。

The wire sizing method is an efficient solution to the interconnect optimization under deep submicron technology. In this paper, a multi phase wire sizing algorithm is brought forward to optimize delay, area, and clock skew. First, a sensitivity based algorithm is proposed to optimize the delay of the clock tree. Then an approximate programming is used to solve the area minimization. Finally, some branches width can be resized to reduce skew further. It is shown experimentally that the algorithms presented can solve efficiently the optimization of delay, area, and skew, and the efficiency and accuracy are satisfactory.