摘要
文章主要介绍了MOS器件中边界陷阱的特点、性能、形成机理及对器件性能的影响。给出了二种边界陷阱的理论模型,阐述了它的微观结构,研究发现快、慢二种边界陷阱有着不同的缺陷结构,同时还讨论了C-V测试技术和DTBT测试技术二种测量边界陷阱的方法,最后论述了边界陷阱的退火效应以及与界面态陷阱和氧化物陷阱的联系与区别,并对所得出结果进行了讨论。
This paper mainly introduce the characteristic, properties and forming mechanism of border traps and their effects on MOS devices performance reported abroad. Two kinds of theoretical models for border traps and their possible microscopic natures are presented. It is shown that the effect are different for fast border traps and slow border traps. Two measuring techniques C-V test and DTBT for border traps are discussed. Finally, border traps annealing effects and their correlation with oxide traps and interface traps are demonstrated.
出处
《微电子学与计算机》
CSCD
北大核心
2000年第4期37-41,共5页
Microelectronics & Computer