基于FPGA的HDLC规程模块实现

Implementation of HDLC Procedures Module Based on FPGA

介绍了高级数据链路控制(HDLC)规程和3种实现HDLC规程的方法。使用VHDL语言在嵌入了NiosⅡ内核的现场可编程门阵列(FPGA)中实现了HDLC规程。说明了HDLC规程模块中发送模块、接收模块的工作流程及配置寄存器模块的用途,着重介绍了HDLC规程模块中最重要的循环冗余校验码(CRC)校验模块及"0"比特的插入删除模块的实现方法。该模块设计结构简单,性能可靠,具有可移植性和可测试性。

The High-Level Data Link Control （HDLC） procedures and three implementation methods of HDLC procedures are introduced. The HDLC procedures are implemented in Field Programmable Gate Array （FPGA） with Nios Ⅱ software core by using VHDL language. The work process of transmitting module and receiving module and the purpose of configuration register module in the HDLC procedures module are introduced. This paper emphatically describes the implementation methods of cyclic redundancy code （CRC） verification module and ＂0＂ bit insertion and deletion module. The module structure is simple and reliable with portability and testability.