Verilog HDL语言RTL级描述的可综合性

The Synthesizability of Verilog HDL at the RTL Level Description

所谓逻辑综合就是将较高抽象层次的描述自动转换到较低层次描述的一种方法 .由于Verilog HDL( Verilog Hardware Description L anguage)本身的特点 ,许多面向仿真的语句虽符合语法规则却是不能综合的 ,这在设计中必须加以避免 .同时讨论了如何写出 Verilog HDL可综合风格的 RTL( Register Transfer Level)

Synthesis is a procedure which transforms a high level of abstraction into a lower level description. At present, synthesis tools transform a structural description of RTL(Register Transfer Level) into Gate Level Netlist. The Verilog HDL language is structured and procedural, like the C programming language, Some statements and structures based on simulation and suited to syntax can′t be transformed into logic unit. So we should avoid those statements and structures which can′t be supported by synthesis tools.We present the basic approach to design program which can be synthesized at the RTL level description of Verilog HDL.