存储器管理部件的研究

Research of Memory Management Unit (MMU)

存储器管理部件 MMU( memory managementunit)的速度直接影响微处理器的性能 ,提高存储器管理部件的速度是本文的设计目标。文中提出了存储器管理部件 MMU设计方法 ,论述了虚拟地址空间映射到物理地址空间逻辑关系 ,确定了 MMU是由暂存器、加法器、段测试电路、高速缓存器 CACHE和地址锁存器 latcher组成 ,给出了 MMU的数据通路和控制通路。经 EDA工具Synopsys仿真 ,结果显示传送于数据通路上的三种类型的操作数在控制流的作用下形成物理地址的时间是 1 .6个处理器周期 ,低于微处理器的最短存储器访问周期 ( 2 )

How to speed MMU (Memory Management Unit) is a key to improve the performance of microprocessor. In this paper, we propose a new architecture of MMU. This architecture is composed of adder, cache, temporary register, segment test circuit and address latch as shown in Fig.2. The physical address is formed by the addition of segment base and offset. The offset can be a single operand, or the addition of two or three operands. In subsection 2.1 and 2.2, we established the data pass and control pass to meet the needs of the formation of the physical address. We carried out simulation of the MMU by Synopsys VSS, it takes 1.6 CPU cycles for the MMU to form physical address from logical address, which is less than the shortest time of memory access (2 CPU cycles).