600MHz CMOS锁相环频率综合器设计

A Design of 600MHz CMOS PLL/Frequency Synthesizer

采用0.6μm CMOS工艺,设计完成600MHz锁相环型频率综合器。以电荷泵型锁相环的线性数学模型为理论依据,依次设计鉴频鉴相器,电荷泵,环路滤波器,电流饥饿型压控振荡器,分频器等模块电路。仿真结果表明,整个系统锁定所需时间为1μs,稳定输出频率640MHz。验证了在普通CMOS工艺条件下,可以设计出性能稳定,工作频率较高的频率综合器。

A 600MHz PLL/frequency synthesizer is designed in 0.6μm CMOS technique. Based on the linear mathe- matical model of the charge pump type of PLL, the circuits, including phase frequency detector, charge pump, loop filter, thecurrentstarved voltage-controlledoscillator and frequency divider, are designed. Simulation results show that the entire system requires lμs to lock, and that the system outputs 640MHz stably. It verifies that a frequency syn- thesizer with stable performance and high output frequency can be designed in ordinary CMOS process.