摘要
针对无源超高频射频识别标签芯片的应用需求设计了一种非易失性存储单元及其灵敏放大电路。该存储单元包括了两个浮栅节点并利用隧道效应(FN)隧穿机制来实现电子向浮栅的注入和擦除,因此其具有较低的编程功耗和较高的数据存储可靠性。为了减小存储单元的面积并进一步降低编程功耗,还采用了厚度仅为4 nm的栅氧作为隧穿结。此外,还设计了一种适合于该存储单元的灵敏放大电路,不仅可以读取存储数据,还可配合存储单元进行数据的擦写操作,从而简化存储单元的设计。基于0.18μm单多晶硅标准CMOS工艺实现了该存储单元及其灵敏放大电路,其单元面积仅为108μm2,经测试表明该存储单元可配合灵敏放大电路实现数据的正确读写,编程电压约为6 V,在擦写次数达到10 000次后,仍具有1.5 V的阈值窗口。
A non-volatile memory cell with the sensitive amplifier circuit was designed for the passive ultra-high frequency(UHF)radio frequency identification(RFID)tag chip.The cell was designed to improve its reliability with double floating gates.Fowler-nordheim(FN)tunneling mechanism was applied for erasing/injecting electrons from/into the floating gates to reduce the program power consumption and increase the data storage reliability.Gate oxide with the thickness of 4 nm was used as the tunneling junction to reduce its area and power consumption.Furthermore,a special sensitive amplifier circuit was desgined,which can read and store the data and can assist the storage cell to erase data,so as to simplify the design of storage cell.The memory cell with the sensitive amplifier circuit was implemented in a 0.18 μm single-poly standard CMOS process.The area of the memory cell is 108 μm2.The measured results indicate that the cell operates well with the sensitive amplifier circuit during read/write operation,and the program voltage is about 6 V.The threshold voltage window of 1.5 V has been observed after the cell was programmed for 10 000 cycles.
出处
《半导体技术》
CAS
CSCD
北大核心
2013年第6期413-418,共6页
Semiconductor Technology
基金
国家科技支撑项目(2012BAH20B02)
国家高技术研究发展计划(863)资助项目(2012AA012301)
国家科技重大专项(2012ZX03004007-002)