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基于VMM的LTE小区搜索模块验证 被引量:1

Cell search module verification based on VMM
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摘要 随着芯片设计规模和复杂度的增加,功能验证变得越来越复杂,验证面临着诸多挑战。有统计数据显示,验证工作占整个设计开发工作60%~80%的时间。在长期演进系统(long term evolution,LTE)中,小区搜索是一个非常关键的过程,是移动终端开机后首先要做的步骤。小区搜索的性能好坏直接影响LTE系统后续过程的进行,对LTE系统的性能有很大的影响。以LTE系统小区搜索模块为例,简要介绍了VMM(verifacation methodology man-ual)验证方法学,并基于VMM验证方法学搭建了小区搜索模块验证平台,对小区搜索模块进行了全面的功能验证。验证结果表明,本模块能够完成预期的目标,采用VMM验证方法学可以极大地提高验证效率,缩短验证周期。 With the growth of the scale and complexity of the chip design, function verification becomes more and more complicated, and verification is confronted with some challenges. Statistical data shows, the work of verification accounts for sixty to eighty pewent of the time for the whole design and development work. In the LTE system, the cell search is a key process, and it is the first process when UE is booting. The performance of cell search influences directly the following process of the LTE system. It has a great influence on the performance of the LTE system. This paper takes cell search module as the example, introduces the VMM verification methodology briefly, and uses VMM verification methodology to build the verification platform of cell search module, and does a comprehensive functional verification for cell search mod- ule. Verification resuhs show that this module will be able to accomplish the desired objectives; using VMM verification methodology greatly improves the efficiency of verification, shortened the verification period.
作者 郭旭 郑建宏
出处 《重庆邮电大学学报(自然科学版)》 CSCD 北大核心 2013年第3期300-304,340,共6页 Journal of Chongqing University of Posts and Telecommunications(Natural Science Edition)
基金 新一代宽带无线移动通信网国家科技重大专项(2011ZX03001-001-02)~~
关键词 VMM方法学 SYSTEMVERILOG 小区搜索 验证 verifacation methodology manual(VMM) methodology SystemVerilog cell search verification
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参考文献8

  • 1CHRIS Spear.SystemVerilog for Verification [M] .NewYork:Springer,2006:1-18.
  • 2JANICK Bergeron,EDUARD Cemy,ALAN Hunter.Veri-fication Methodology Manual for System Verilog [ M].New York:Springer,2005:10-16.
  • 3钟文楓.SystemVerilog与功能验证[M].北京:机械工业出版社,2010:5-9.
  • 4Accellera Organizationtion.SystemVerilog3.1 a LanguageReference Manual Accellera,s Extensions to Verilog[M].California; Accellera,2004:30-45.
  • 5BERGERON Janick.Writing Testbenches using SystemVerilog[ M].New York:Springer,2006:5-8.
  • 6杨鑫,徐伟俊,陈先勇,夏宇闻.System Verilog中的随机化激励[J].中国集成电路,2007,16(10):37-41. 被引量:6
  • 7ANDREW Piziali.Functional Verification CoverageMeasurement and Analysis [ M] .New York:Kluwer Ac-ademic Publisher,2004:13-15.
  • 8方颖立.基于VMM的寄存器抽象层验证[J].电子设计技术 EDN CHINA,2007,14(8):110-111. 被引量:5

二级参考文献3

  • 1[1]IEEE Std 1800TM-2005 IEEE Standard for SystemVerilog-Unified Hardware Design,Specification,and Verification Language
  • 2[2]Janick Bergeron & Eduard Cerny & Alan Hunter & Andrew Nightingale 《 Verification Methodology Manual for SystemVerilog》 Springers 2006 Synopsys,Inc and ARM Limited
  • 3[3]《Verification Methodology Manual Tutorial 》 2006.6Synopsys Inc

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