摘要
时序逻辑电路的次态卡诺图综合设计法 ,是将有关信号的下降沿或上升沿用箭头在次态卡诺图中标示出来 ,并根据化简需要填出各约束项的次态取值 ,从而将时钟信号的选取和自启动的检验合并在次态卡诺图中进行的 1种新的设计方法 .
The Next-State Karnaugh Map comprehensive design is a new design.We use arrowheads to show the degressive and ascendant of the messages concerned in the Next-State Karnaugh Map and fill in with sub_cost of each restrained nape in needs of epitomization and so put the clock signal and the check of automotion together in the Next-State Karnaugh Map.
出处
《四川师范学院学报（自然科学版）》
2000年第3期296-300,共5页
Journal of Sichuan Teachers College(Natural Science)
关键词
时序逻辑电路
次态卡诺图
综合设计法
sequential logic circuit
Next_State Karnaugh Map
comprehensive design
clock signal
