期刊文献+

大电流,微功耗,小体积单片LDO的设计与实现 被引量:1

Design and implementation of high current micro-power monolithic LDO with small size
下载PDF
导出
摘要 以设计输出电流为700 mA,静态电流为50μA,芯片面积为1.5 mm×2.0 mm的LDO线性稳压器为目标,提出的LDO电路利用基准电路的输出直接作为芯片的输出,用基准电路所固有的跨导放大器对输出进行检测并反馈至单级放大器,放大后输出至功率管的基极,控制功率管输出额定的电压和电流。无需冗余的误差放大器,使得环路补偿极为简单,不存在传统LDO的补偿难题。在电路上把传统LDO电路所需各个模块的功能糅合到了一个较为简单的电路中,大大减小了芯片面积,并且减小了静态电流。对电路进行了仿真分析并采用2μm 36 V Bipolar工艺生产实现,流片后的测试结果表明该芯片实现了大电流,微功耗,小体积的特性。 A low-dropout regulator (LDO) with an output current of 700 mA, quiescent current of 50 μA and chip area of 1.5 mm×2.0 mm is proposed. The LDO circuit takes reference circuit output as its chip output. The inherent transconductance amplifier of reference circuit is used to detect the output and feedback to stage amplifier, the signal is output to the base of power transistor after amplified, which could control the power valve output rated voltage and current. The error amplifier without redundancy makes the loop-compensation extremely simple, excludes the compensation problems in traditional LDO circuit. The function of each module which traditional LDO needs is mixed into an easier circuit, thus the chip area and the quiescent current are greatly reduced. The simulation analysis of the circuit is conducted, and realized by 2 μm 36 V Bipolar technology, the tapeout result shows that the chip has the characteristic of high-current, micro-power and small size.
机构地区 北京工业大学
出处 《现代电子技术》 2013年第13期150-153,共4页 Modern Electronics Technique
基金 国家自然科学基金(60976028) 国家自然科学基金(61204040) 北京市自然科学基金(4123092) 教育部博士点基金(20121103120018)资助
关键词 线性稳压器 大电流 低功耗 跨导放大器 BIPOLAR linear voltage regulator high-current low power consumption transconductance amplifier Bipolar
  • 相关文献

参考文献9

  • 1王忆,何乐年.CMOS低压差线性稳压器[M].北京:科学出版社,2012.
  • 2KWOK K C, MOK P K T. Pole-zero tracking frequency com-pensation for low dropout regulator [C]// Proceedings of 2002IEEE International Symposium on Circuits and Systems. Phoe-nix, Scottsdale, USA; IEEE, 2002: 735-738.
  • 3RINCON-MORA G,ALLEN P E. A low voltage, low quiescentcurrent, low drop-out regulator [J]. IEEE Journal of Solid-StateCircuits, 1998,33(1): 36-44.
  • 4LEE H, MORK P K T, LEUNG K N. Design of low power ana-log drivers based on slew - rate enhancement circuits for CMOSlow-dropout regulators [J]. IEEE Transactions on Circuits Sys-tems II: Express Briefs, 2005,52(9): 563-567.
  • 5GRAY P R,HURST P J, LEWIS S H.模拟集成电路分析与设计[M].张晓林,译.4版.北京:高等教育出版社,2005.
  • 6LEUNG K N, MORK P K T. A CMOS voltage reference basedon weighted AVcs for CMOS low - dropout linear regulators [J],IEEE Journal of Solid-State Circuits, 2003 , 38(1): 146-150.
  • 7OR P Y, LEUNG K N. An output - capacitorless low - dropoutregulator with direct voltage-spike detection [J]. IEEE Journalof Solid-State Circuits, 2010,45(2) : 458-466.
  • 8GUO J P, LEUNG K N. A 6 jxW chip-area-efficient output-ca-pacitorless LDO in 90 nm CMOS technology [J]. IEEE Journalof Solid-State Circuits, 2010, 45(9) : 1896-1905.
  • 9MAN T Y, LEUNG K N. Development of single-transistor-controlLDO based on flipped voltage follower for SoC [J]. IEEETransactions on Circuits and Systems I : Regular Papers,2008,55(5): 1392-1401.

共引文献2

同被引文献5

引证文献1

二级引证文献3

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部