复数乘法运算的优化方法研究与实现

Study and implementation of optimized methods of complex multiplication

传统的复数乘法器实现需要4个乘法器和2个加法器。在现场可编程门阵列(FPGA)中乘法器资源是非常宝贵的,因此,给出了两种复数乘法的优化算法,一种方法可以节省25%的乘法器资源,另一种可以节省50%的乘法器资源,而且其实现架构可以使用流水线满足高速数字信号处理的要求。同时,还给出了数字信号处理中常用的有限冲激响应(FIR)滤波器和共轭复乘的优化实例。

The implementation of traditional complex multiplier needs 4 multipliers and 2 adders. Muhipliers are very precious in FPGA. This paper gives two optimized methods for complex multiplication. One method can save 25% of the multiplier; the other can save 50%. Also the optimized implementation structure can support high-speed requirements with pipeline in digital signal processing. At the same time, this paper gives the optimized example of FIR filters and conjugate complex multiplication.