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一种低功耗CMOS晶振电路设计 被引量:3

A Design of Low Power CMOS Crystal Oscillator Circuit
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摘要 在组成反相器的两个晶体管的栅端添加一个串联电容,直流通过连接在反相器内部的大电阻偏置这两个晶体管,P管被低于电源电压一个阈值的电压偏置,N管被高于低电压一个阈值的电压偏置,偏置电压通过电流镜镜像,因此受温度和工艺的影响较低。一种低功耗CMOS晶体振荡电路利用上述反相器,它的开启电压低于P管和N管的阈值之和,整体电路消耗的电流大概为传统电路的1/5。此晶振电路基于MXIC 0.5μm仿真模型验证实现,整体电路消耗的功耗电流小于750 nA。 A CMOS inverter of two-transistors has two transistor gates coupled together by a coupling capacitor. DC gate bias is supplied to each transistor through high value resistors. The P-channel transistor is biased to a threshold below the power and the N-channel transistor is biased to a threshold above ground. The biasing voltage are developed through the use of a current mirror so that the biasing is independent of processing variables and temperature. A crystal oscillator created using such an inverter and biasing will operate at voltage substantially below sum of P and N thresholds and at a current level about one-fifth of that of a conventional CMOS oscillator. This low power CMOS crystal oscillator circuit was designed based on MXIC's 0.5 μm CMOS process,the current consumption of the whole circuit is under 750 nA.
出处 《电子器件》 CAS 北大核心 2013年第3期336-339,共4页 Chinese Journal of Electron Devices
基金 中国科学技术部国家重大科技项目(20112x05008-005-04-02) 国家自然科学基金项目(61274043) 湖南省自然科学基金重点项目(61233010) 湖南省教育厅科研基金项目(12JJ4064)
关键词 电路设计 CMOS 低功耗 晶振 电压偏置 晶体振荡电路 反相器 串联电容 oscillator circuit coupling cap low power inverter threshold
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参考文献11

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二级参考文献12

共引文献9

同被引文献26

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