基于沟长偏置的近阈值逻辑漏功耗减小技术

Gate-length Biasing for Near-threshold Logic Leakage Reduction

随着集成电路芯片特征尺寸的不断缩小,减小漏功耗已成为集成电路设计技术的焦点之一.在近阈值逻辑电路中,亚阈值漏电流是其最主要漏电流的构成.根据MOS器件沟道长度与亚阈值漏电流之间的非线性关系,通过适度提高MOS器件的沟道长度从而降低CMOS逻辑电路的漏功耗,形成了基于沟长偏置的漏功耗减小技术.应用HSPICE软件对基于45nm PTM工艺参数沟长偏置为8%的基本逻辑门电路、镜像加法器和传输门加法器的漏电流进行了仿真测试,实验结果表明漏电流约下降了39%～44%.因此沟长偏置技术是一种有效的适用于近阈值逻辑的漏功耗减小技术.

With processing chips scaling down,leakage power reduction has become one of the most important design concerns.In this paper,we propose small biases of transistor gate-length to further minimize leakage power based on the fact that the sub-threshold leakage current is the main component of the total leakage in near-threshold logic circuits.Due to the super-linearity between sub-threshold current and gate length,the leakage current reduction can be considerably achieved by slightly increasing the gate-length.Three basic logic gates,a mirror adder and a transmit adder with 8% gate-length biasing are realized and simulated using HSPICE at a 45nm CMOS process with the PTM model.Simulation results show that the leakage current of those circuits is reduced 39%-44% compared with the nominal gate-length ones.Therefore,the gate-length biasing technique is an attractive approach for low leakage near-threshold circuits.