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征兆测试新方法

Novel way of syndrome testing
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摘要 征兆测试和奇偶测试是已经使用多年的基于穷尽输入的固定型故障测试方法。在征兆测试与奇偶测试相结合的基础上,提出了一种新的征兆测试方法,即三阶征兆测试法。本方法的特点在于提高测试效率的同时也提高了征兆测试的故障覆盖率,使得原来征兆不可测的电路也可以进行征兆测试。其主要思想是在传统征兆测试的基础上首先引进奇偶测试,对被测电路进行预处理,提高测试效率;然后,对征兆测试作进一步升华处理,成为二阶、三阶征兆测试,提高测试的故障覆盖率。通过对部分基准电路和常用电路的测试实验验证了所提新方法的实用性和有效性。 Syndrome testing and parity testing are exhaustive input based fixed fault testing methods. They have been employed for many years. The paper proposes a novel syndrome testing method, named third order syndrome testing, which combines syndrome testing and parity testing. Its main feature is that both the testing efficiency and the fault coverage are improved so that syndrome testing can be per- formed on the circuits whose syndrome could not be tested. Based on the traditional syndrome testing, parity testing is introduced to preprocess the circuits drome testing is enhanced to be the second and the thus improving the testing efficiency. Then, syn third order syndrome testing, thus improving the fault coverage. Experiments on reference circuits and commonly used circuits demonstrate the practica bility and effectiveness of the proposal.
出处 《计算机工程与科学》 CSCD 北大核心 2013年第7期6-10,共5页 Computer Engineering & Science
基金 国家自然科学基金资助项目(61076123)
关键词 奇偶测试 征兆测试 二阶 三阶征兆测试 穷尽测试 故障覆盖率 parity test syndrome test second order and third order syndrome testing exhaustivetest fault coverage
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参考文献9

  • 1Savir J. Syndrome-testable design of combinational circuit[J].IEEE Transactions on Computers, 1980,C-29(6) :442-451.
  • 2Savir J. Syndrome-testing of syndrome untestable combina-tional circuit^J], IEEE Transactions on Computers, 1981,C-30(8):606-608.
  • 3Xu Shi-yi. High-order syndrome testing for VLSI circuits[C]//Proc of the 11th IEEE Pacific Rim International Symposi-um on Dependable Computing,2005 : 8-14.
  • 4Gu Su-yun,Xu Shi-yi. A novel approach to syndrome testingof VLSI circuits[J]. Journal of Tsinghua University (Scienceand Technology) , 2011, 51 (SI) : 1499-1504. .
  • 5Armstrong D E. On finding a nearly minimal set of fault de-tection tests for combinational logic nets[J]. IEEE Transac-tions on Computers, 1966,EC-15(1) : 66-73.
  • 6Akers S N. A parity bit signature for exhaustive testing[J].Proc of IEEE International Test Conference, 1988:333-338.
  • 7Wagner K D, Chin C K,McCluskey E J, Pseudorandom tes-tingCJ]. IEEE Transactions on Computers,1987,C-36C3):332-343.
  • 8Xu Shi-yi. Pseudo-parity testing and testable design [C] //Proc of IEEE ATS,05, 2005:354-360.
  • 9顾苏赞,徐拾义.大规模集成电路征兆测试新方法[J].清华大学学报:科学与技术,2011,5HSuppl) :1499-1504.

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