适用于位交叉布局的低电压SRAM单元(英文)

Low Voltage SRAM Cell Suitable for Bit-Interleaved Structure

提出一种9管单端SRAM单元结构,该种SRAM单元采用读写分离方式,具有较高的保持稳定性和读稳定性。该单元采用新的写操作方式,使由其组成的存储阵列中,处于"假读"状态的单元仍具有较高的稳定性,因此在布局时能够采用位交叉布局,进而采用简单的错误纠正码(ECC)方式解决由软失效引起的多比特错误问题。仿真结果显示,当电源电压为300 mV时,该种结构的静态噪声容限为100 mV,处于"假读"状态的单元静态噪声容限为70 mV。

A single-ended nine-transistor （9T） SRAM scheme is proposed for sub-threshold operation. The new SRAM cell provides high stability using disturb-free read operation. With a new write mechanism, the cell can solve the pseudo-read problem. Thus, the bit-interleaved structure can be used to address the multiple bit soft-errors problem. Simulation result shows that the SRAM cell can provide 100 mV read static-noise-margin （SNM） and 70 mV worst half-select SNM, when the supply voltage is 300 mV.