优先级资源共享在RTL综合中的实现

Implementation of Priority Resource Sharing in RTL Synthesis

针对现场可编程门阵列内部复杂算术操作资源有限、资源占用面积较大以及RTL级(寄存器传输级)综合中面积优化大多仅针对一般逻辑操作的问题,提出了一种优先级资源共享方法.该方法通过改进普通的资源共享方法,使不同时刻进行的算术逻辑单元(ALU)按照相同输出、相同输入、无共同端口的优先级顺序依次进行共享.实验结果表明:该方法不仅可以减小ALU的个数,达到面积优化的效果,而且和普通的资源共享方法相比,其所需多路选择器更少,时序结果更好,还能避免数据流冲突.

In the field programmable gate array（FPGA）,the quantity of arithmetic resources which need more area than normal logic resources is limited,and most of the RTL（Register Transfer Level） synthesis algorithms only focus on normal logic resources.In order to solve these problems,a method of priority resource sharing is proposed.This method improves normal resource sharing methods and makes two or more arithmetic logic units（ALUs） operating at different time to share the resources in a priority order of ALUs having the same output,ALUs having the same input and ALUs having different ports.Experimental results show that the proposed method reduces the number of ALUs and implements the area optimization in FPGA;and that,as compared with normal resource sharing methods,it costs less multiplexers,achieves better timing results and avoids data flow conflicts.