二维5/3小波变换在并行计算单元中的设计实现

Design and Implementation for 2-D IWT using Parallel Computing Units

本文提出了一种针对整数二维5/3小波提升算法的并行计算设计方案,其整体结构具有行变换与列变换之间并行计算、数据分组输入、不同行变换(列变换)之间并行计算的特点.文中重点介绍了该小波提升算法的取整处理模式、算法改进和硬件设计实现等方面.本文结构平均每周期输出2个变换结果,完成对N×N大小图像的处理需花费大约N2/2个时钟周期,同时在FPGA中实现最高同步时钟频率394.

In this paper,a novel design and hardware implementation using parallel computing for 2-D integer lifting wavelet transform（IWT）is proposed of which input datas are divided into groups,its row and column transform module use parallel computing technology.This design is capable to produce 2results every cycle,which takes N2/2time units to finish a N×N 2DIWT.And also,we implemented it in FPGA,the estimated frequency of operation is 394.415MHz.