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基于VPR的FPGA布局算法的改进 被引量：1

Improvement of FPGA Placement Algorithm Based on VPR
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摘要 通过在原模拟退火算法中加入回火过程对原算法进行优化,同时,减小内循环次数用于弥补回火导致的布局时间增量.回火过程用于寻找"被遗漏"的最优解.结果表明新算法利于跳出局部最优"陷阱",进一步搜索最优解,具体体现在改进后的算法不但能够保证布局质量,而且缩减了布局时间,同时,布线时间与电路关键路径延时得到不同程度的改善. In this paper,adding the tempering process to the original algorithm and reducing the number of inner loop to compensate for layout delay increments due to tempering.This process is used to find better placement that haven been abandoned before.The results show that the new algorithm is conducive to jump out of the local optimum＂trap＂,search for the optimal solution.In detail,the improved algorithm not only keep good placement results,but also largely reduce layout time,at the same time,routing time and critical path delay also have been reduced.
作者 杜星格 袁小龙 余明
机构地区 北京交通大学电子信息工程学院
出处 《微电子学与计算机》 CSCD 北大核心 2013年第7期64-67,共4页 Microelectronics & Computer
基金 国家自然科学基金(61076034) 中央高校基本科研业务费专项资金(2011JBZ002)
关键词 现场可编程门阵列 模拟退火算法 通用布局布线工具 FPGA布局算法 回火过程 退火表 FPGA simulated annealing algorithm VPR FPGA placement algorithm tempering process annealing table
分类号 TP312 [自动化与计算机技术—计算机软件与理论]
  • 相关文献

参考文献10

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二级参考文献9

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共引文献1

同被引文献10

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微电子学与计算机
2013年 第7期

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