弱对偶基下RS码译码方法的研究

Decoding method for RS codes in weakly-dual-basis

讨论了高速 RS码译码器的设计问题。研究了有限域元素在弱对偶基 (WDB)下的表示 ,基于弱对偶基下的最优弱对偶基的计算方法 ,给出了有限域比特并行乘法器的设计 ;采用了一种可以避免求逆运算的修正 BM迭代算法 ,并且利用这样的迭代算法和基于弱对偶基的比特并行乘法器构成了广泛应用的 RS码的译码器。对译码器定量分析的结果表明 :弱对偶基下比特并行乘法器设计复杂度降低 ,便于VL SI实现 ;修正 BM迭代算法使得简单的硬件实现成为可能 ,且有利于 On-The-Fly纠错。译码器的数据吞吐率可达较高值 。

The design problem of the high speed RS decoder is discussed. The presentation of the finite field elements in WDB is studied. And based on the computing method for the optimum WDB, the design for the bit parallel multiplier of finite field is presented. By selecting the bit parallel multiplier based on WDB and the modified BM iterative algorithm that can avoid inversion, the widely used RS decoder is constructed. The analysis results indicates: the complexity of the bit parallel multiplier is low and is suited for VLSI implementation; the modified BM iterative algorithm makes the simple hardware implementation possible and is advantageous to On The Fly error correcting. The throughout of the decoder can reach a high value and it is suited for the high speed application.