一种结构新颖的流水线Booth乘法器设计

A Novel Structure of the Pipelined Booth Multiplier

在对传统Booth乘法器研究的基础上,介绍了一种结构新颖的流水线型布什(Booth)乘法器。使用基-4 Booth编码、华莱士树(Wallace Tree)压缩结构、64位Kogge-Stone前缀加法器实现,并在分段实现的64位Kogge-Stone前缀加法器中插入4级流水线寄存器,实现32 t×32 bit无符号和有符号数快速乘法。用硬件描述语言设计该乘法器,使用现场可编程门阵列(Field Programmable Gate Array,FPGA)进行验证,并采用SMIC 0.18μm CMOS标准单元工艺对该乘法器进行综合。综合结果表明,电路的关键路径延时为3.6 ns,芯片面积<0.134 mm2,功耗<32.69 mW。

On the basis of the research on traditional Booth multiplier,a novel structure of pipelined Booth multiplier is proposed,which is based on radix-4 Booth encoding with Wallace tree compression structure and 64 bits Kogge-Stone prefix adder.The 32 bit×32 bit unsigned and signed rapid multiplication is realized by inserting 4-level pipeline registers in segment achieved 64 Kogge-Stone adder.The design is described in Hardware Description Language（HDL） and verified by Field Programmable Gate Array（FPGA）.Then,the multiplier is synthesized by SMIC 0.18 μm CMOS process.Synthesis results show that the circuit＇s critical path delay is 3.6 ns,the chip area is less than 0.134 mm2,and the power consumption is less than 32.69 mW.