基于FPGA的LDPC编码实现与验证

Implementation and Verificationof LDPC Coding Based on FPGA

介绍数字电视传输系统中LDPC编码设计及FPGA实现与验证,传输系统中采用了基于准循环LDPC码结构,其校验矩阵具有准循环特性。编码时需求出具有准循环特性的生成矩阵,即可利用移位寄存器进行编码,将循环移位得到的矩阵存储到RAM中,节约了存储矩阵空间;运算模块采用流水线方式运算,节约了硬件资源。利用Quartus II仿真平台进行了测试、综合和仿真,再下载到Stratix II EP2S60F1020C3 DSP Develoment Ezki硬件平台调试运行得到编码结果,并与Matlab建模仿真结果进行比较,验证了其实现过程的正确性。

This paper describes LDPC coding design in the digital television transmission system and FPGA implementation and verification.LDPC code is based on the structure of quasi-cyclic LDPC code in the transmission system,and the check matrix is quasi-cyclic characteristic.The encoding needsagenerator matrixhavingaquasi-cycle characteristics,whichcanbe encodedusing a shift register andthe obtained by the cyclic shiftmatrix isstoredinto the RAM,andsavesthe space requiredofthememory matrix;thepipelinedoperationinthearithmetic modulesaves hardware resources.Then throughQuartus IIsimulation platform,testing、synthesis and simulation is done,and the LDPC code is debugin theStratix II EP2S60F1020C3 DSP Develoment Ezkihardware platformto runcodedresults.Finally,comparedto theMatlabmodelingsimulationresultsto verifythecorrectnessoftheimplementation process.