基于SMIC40LL工艺的DDR物理层IP设计

随着高性能消费电子如智能手机,平板电脑的迅速普及,对高性能低功耗的DDR接口电路的需求随之迅速增加。本文论述了在SMIC40LL工艺上实现了高性能、低功耗、小面积的DDR物理层IP技术,包括DDR物理层架构、DLL设计、IO设计和物理实现。该物理层IP可以在SS条件下达到1333Mbps的速率并在核心电压稍稍过压下达到1600Mbps的速率。

With the rapid growth of high performance consumer electronic devices, such as smart phone, PAD, etc. there are increasing demand for high performance, low power DDR interface circuit. This paper addresses the design of high performance, low power, small area PHY IP on SMIC40LL process, including DDR PHY architecture design, DLL design, IO design, and physical implementation. The PHY IP can run at 1333Mbps under SS corner and can work at 1600Mbps with a little bit overvoltage of the core power.