CAN总线控制器IP核设计实现

Design and Implementation of CAN Bus Controller IP

CAN总线是一种成熟的串行通信总线,它具有可靠性高、稳定性好、抗干扰能力强、通信速率高、维护成本低、实时性强、很好的开放性及数据兼容性等优点。CAN总线这些众多的优点使其广泛应用于工业自动化控制等领域。其应用的广泛性则进一步对CAN总线IP提出了需求。同时以IP实现的CAN总线控制器所具有的通用处理器访问接口,良好的可移植性等优点使其可以集成于各种嵌入式SoC设计中。文中从CAN总线的规范和特点出发,提出了CAN总线控制器IP核的特点并定义了其功能,采用Verilog语言设计实现了CAN总线控制器IP核的功能,最后通过仿真和FPGA原型验证,证明了设计实现的正确性。目前CAN总线控制器IP核已经应用于SOPC和SoC的嵌入式应用设计中。

CAN Bus had been considered as a kind of mature serial communication bus because of its highly reliability, better stability, strong capacity of resisting disturbance, high communication rate, low costing of maintaining and also benefited in strong real-time, good opening data sharing and so on. Due to its wide application, the extended demands would be proposed either. The CAN bus controller could be implemented into various of embedded SoC system based on CAN bus controller IP＇ s advantages in its general processor access interface, good transportability. Proposed the function and character of CAN bus controller IP core and achieved the function of CAN con- troller with help of Verilog language based on the features of CAN bus protocol. According to simulation and FPGA verification, the de- sign had been proved as correct at last. Nowadays, CAN bus controller IP core had been widely used in SOPC and SoC embedded design and implementation.