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典型可重构架构的算法映射分析 被引量:1

Analysis of Mapping Algorithms on Typical Reconfigurable Architectures
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摘要 可重构架构高效、灵活,能够满足嵌入式处理领域的高性能需求.通过对三种粗粒度与两种多粒度的典型可重构架构进行建模,将算法分类,并映射不同类型的算法到可重构架构上,从硬件利用率,计算时间,输入输出带宽,数据组织形式,数据复用率等五个方面进行分析,得到多粒度的可重构架构,配以灵活的互联能够更好地完成各类算法,但是总体的硬件利用率较低.而数据带宽仍然是可重构架构的瓶颈.为可重构架构设计提供理论依据. Reconfigurable architectures,which are efficient and flexible,can meet the high performance needs of embedded processing field.This paper models three coarse-grained and two multi-grained typical reconfigurable architectures,then classifies algorithm and maps different types of algorithm on the reconfigurable architectures.Analysis has five parts: hardware utilization,computing time,input and output bandwidth,data arrangement and data reuse rate.Conclusion is that multi-grained reconfigurable architecture with flexible interconnect can perform different algorithms better,however,hardware utilization rate is a little lower.Data bandwidth is still the bottleneck of reconfigurable architectures.Provide theoretical basis for later design of reconfigurable architectures.
出处 《微电子学与计算机》 CSCD 北大核心 2013年第8期160-164,168,共6页 Microelectronics & Computer
关键词 可重构架构 粗粒度 多粒度 计算密集型 I/O密集型 算法映射 reconfigurable architecture coarse-grained multi-grained CPU-bound I/O-bound algorithm mapping
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参考文献10

  • 1李仁发,周祖德,陈幼平,徐成,李方敏.可重构计算的硬件结构[J].计算机研究与发展,2003,40(3):500-506. 被引量:27
  • 2Huynh H P,Mitra T. Runtime adaptive extensibleembedded processors 一 a survey[C]//Int’l Conf onEmbedded computer Systems, Architectures,Model-ing and Simulation (SAMOS). [S. L. ]. IEEE, 2009:215-225.
  • 3Vassiliadis S, Soudris D. Fine- and coarse-grain recon-figurable computing [M]. [BerLin]. Springer, 2007:918-978.
  • 4Ahmed W,Shafique M, Bauer L, et al. mRTS: run-time system for reconfigurable processors with multi-grained instruction - set extensions[C]//Proceedingsof the 14th conference on Design, Automation andTest in Europe (DATE) Washington, DC, USA:IEEE, 2011:1554-1559.
  • 5Mei B. Adres: an architecture with tightly coupledVLIW processor and coarse-grained reconfig - urablematrix[C]//Proc Field-Programmable Logic and Ap-plications (FPL 03). BerLin:Springer, 2003:61 - 70.
  • 6Baumgarte V,Mayr F, Niickel A, et al. Wein -hardt : PACT XPP - a self - reconfigurable data pro-cessing architecture[J]. The Journal of Supercomput-ing, 2003(26): 167-184.
  • 7Hartej Singh. Morphosys : an intergrated reconfigu-rable system for data - parallel and computation-in-tensive applications [J]. IEEE Transactions on com-puters ,2000,49(5):56-61.
  • 8Putzke - roming W. MORPHEUS architecture over-view[J]. Dynamic System Reconfiguration in Hetero-geneous Platforms-The MORPHEUS Approach,2009,40(3):31-37.
  • 9KOnig R, Bauer L, Stripf T, et al. KAHRISMA: anovel hypermorphic reconfigurable-instruction-setmulti-grained-array architecture [C]//Proc DATE.[S. L.].IEEE, 2010:819-824.
  • 10Gray J. Distributed computing economics[J]. Distribu-ted Computing Economics ACM Queue, 2008,6(3):63-68.

二级参考文献26

  • 1S Hauck, Z Li, E Schwabe. Configuration compression for the Xilinx XC6200 FPGA. In: IEEE Symp on Field-Programmable Custom Computing Machines. New York: IEEE Press, 1998
  • 2Patterson. Computer Architecture. San Francisco, CA: Morgan Kaufmann, 1999
  • 3Katherin Compton. Reconfigurable Computing. http//www.ee.washington.edu/hauck
  • 4M Rencher, B L Hutchings. Automated target recognition on SPLASH2. In: IEEE Symp on Field-Programmable Custom Computing Machines. New York: IEEE Press, 1997
  • 5M Weinhardt, W Luk. Pipeline vectorization for reconfigurable systems. In: IEEE Symp on Field-Programmable Custom Computing Machines. New York: IEEE Press, 1997
  • 6S Hauck, W D Wilson. Runlength compression techniques for FPGA configurations. Northwestern University, Dept of ECE, USA, Tech Rep, 2001
  • 7P Graham, B Nelson. Genetic algorithms in software and in hardware-A performance analysis of workstation and custom computing machine implementations. In: IEEE Symp on FPGAs for Custom Computing Machines. New York: IEEE Press, 1996
  • 8The Programmalbe Logic Data Book. San Jose, CA: Xilinx Inc, 1994
  • 9XC6200: Advanced Product Specification. San Jose, CA: Xilinx Inc, 2001
  • 10Data Book. San Jose, CA: Altera Corporation, 2001

共引文献26

同被引文献8

  • 1沈启峰,黄士坦,杨靓.AES中有限域运算的优化及算法高速实现[J].微机发展,2005,15(12):15-17. 被引量:4
  • 2NIST. FIPS PUBS 197. NIST Specification for the ad- vanced encryption standard (AES)[S]. USA: NIST, 2001.
  • 3IETF network working group. RFC2401. Security ar- chitecture for the internet protocol [S]. USA: IETF, 1998.
  • 4Daemen J,Rijmen V. AES Proposal: Rijndael, NIST AES Proposal[EB/OL]. [2014-12-15]. http://csm nist. gov/ar- chive/aes/rijndael/Rijndael-arrmaended, pdf.
  • 5Good T, Benaissa M. AES on FPGA from the fastest to the smallest [C] // Sunar B. Cryptographic Hardware and Embedded Systems (CHES). Edinburgh, Scotland: Springer-Verlag, 2005 : 427-440.
  • 6Garcia A, Berekovic M, Aa T. Mapping of the AES cryptographic algorithm on a coarse-grain reconfigu- rable array processor[C]//Verkest D. International Conference on Application-Specific Systems, Architec- tures and Processors (ASAP). Leuven, Belgium: IEEE Press, 2008 : 245-250.
  • 7Mucci C, Vanzolini L,Lodi A, et al. Implementation of AES on a dynamically reconfigurable architecture[C]//IEEE. Design, Automation & Test in Europe Con- ferenee Exhibition (DATE). Nice Acropolis, France:Curran Associates, Ine,2007:355-360.
  • 8彭浩,刘恺,张亮,廖望,戴葵.轻量级AES加解密芯片设计与实现[J].微电子学与计算机,2014,31(8):94-97. 被引量:5

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