锂掺杂氧化锌薄膜晶体管的研究

Preparation and Characterization of Li-Doped ZnO Thin Film Transistors

采用溶胶凝胶法(sol-gel)在P型硅基底制备了锂掺杂氧化锌薄膜.以锂掺杂氧化锌薄膜为沟道层,制备了底栅结构的薄膜晶体管.XRD实验结果表明,500℃退火得到的锂掺杂氧化锌薄膜为纤锌矿结构,具有c轴择优取向.SEM实验结果说明,薄膜晶粒大小约为25nm,尺度分布均匀.电学测试结果显示器件是N沟道增强型.

Li-doped ZnO （ZLO） films were prepared by sol-gel technique on P-type silicon. With ZLO films as channel layers, bottom gate thin film transistors were fabricated. The XRD results showed the ZLO films were wurtzite structure with c-axis orientation at the heat-treatment of 500℃ . The SEM experiments indicated that the ZLO films were uniform and the grain size was about 25 nm. The I-V property of ZLO- TFTs implied the devices were N-channel enhanced thin film transistors.