用于5.8GHz ETC超低功耗唤醒接收机模拟前端

Ultra-Low Power Analog Front End of Wake-up Receiver for 5.8 GHz ETC

基于5.8 GHz电子不停车收费系统(electronic toll collection,ETC)应用,介绍了射频收发芯片中唤醒接收机(wake-up receiver,WuR)的模拟前端电路。采用了一种共源共栅结构的射频包络检波器(RF envelop detector,RFED)并分析了其频率转换机制,利用亚阈值偏置技术,实现了高电流效率和高频率转移效率。设计了具有带通滤波特性的可编程增益放大器(PGA)、带迟滞功能的比较器以及电流基准源等子电路。电路基于TSMC 0.18μm CMOS工艺制造,占用芯片面积约为430μm×300μm。实测结果表明,在3.3 V电源供电条件下,模拟前端电路仅消耗2.5μA电流,实现了-45 dBm的唤醒接收灵敏度,满足ETC WuR的设计指标和实际应用需求。

A wake-up receiver （WuR） analog front end for the 5.8 GHz electronic toll collection （ETC） transceivers was presented. A cascode structure based on RF envelop detector （RFED） was adopted and the frequency transforming mechanism was analyzed. The high current efficiency and frequency transforming efficiency were achieved due to the sub-threshold region biasing technology. A baseband programmable gain amplifier （PGA） with band-pass filter characteristic, a hysteresis comparator and a current reference were also designed. The circuit was fabricated based on the TSMC 0. 18 μm CMOS process, the analog front end occupies a die area of 430 μm × 300 μm. The measurement results show that a sensitivity of -45 dBm is achieved with power consumption of 2.5 μA from a 3.3 V DC source, which satisfies the design specification and meets the practical demands for ETC WuRs.