摘要
提出了一种基于混合集成电路工艺制作的小型化取样锁相介质振荡器(PDRO)的设计方法。对取样鉴相电路与脉冲形成电路进行了理论分析,并深入探讨取样锁相技术原理,保证近端低相噪要求。采用自主设计的负阻GaAs HBT MMIC作为振荡源,解决了用分立器件难于调试的问题,并实现了宽调谐带宽、低相位噪声,从而取消了调谐螺钉,达到了较高的稳定性和可靠性。应用ADS、Multisim软件对介质振荡器、环路滤波器进行了仿真设计,最终完成了频率0.500~40 GHz、小型化、系列化PDRO的研制,频率为9 GHz时PDRO实测试结果显示:输出功率17 dBm,杂波抑制大于75 dBc,相位噪声为-115 dBc/Hz@1 kHz,-125 dBc/Hz@10 kHz,-125 dBc/Hz@100 kHz,-144 dBc/Hz@1 MHz,外形封装尺寸为40 mm×40 mm×12.8 mm。
Based on hybrid integrated circuit technology, a method of designing the miniature sampling phase locked dielectric resonator oscillator (PDRO) was proposed. Theory of sampling phase detector and pulse formation circuit was analyzed, the principle of sampling phase locked loop in depth was discussed, and the requirement of near carry low phase noise was ensured. The negative resistance GaAs HBT MMIC of independent design was adopted on oscillatory source, which solved the difficulties in adjusting of discrete devices, carried out wide tuning bandwidth and low phase noise, and higher stability and credibility were achieved without tuning screws. Simulations of ADS and Multisim software were used in the design of the dielectric resonator oscillator and loop filter. A series of mini-packaged PDRO were developed which frequency covers from 500 MHz to 40 GHz. The test results of 9 GHz PDRO show that the output power is 17 dBm at 9 GHz, the spurious rejection radio is more than 75 dBc, the phase noises are -115 dBc/Hz@ 1 kHz, - 125 dBc/Hz@ 10 kHz, - 125 dBc/Hz@ 100 kHz, - 144 dBc/Hz@ 1 MHz, the outline dimension is 40 mm ×40 mm × 12. 8 mm.
出处
《半导体技术》
CAS
CSCD
北大核心
2013年第7期502-505,509,共5页
Semiconductor Technology
关键词
小型化
锁相介质振荡器(PDRO)
相位噪声
取样鉴相器
混合集成
miniature
phase lock dielectric resonator oscillator (PDRO)
phase noise
sampling phase detector
hybrid integrated