新型自对准石墨烯场效应晶体管制备工艺

Novel Fabrication Process for Self-Aligned Graphene Field-Effect Transistors

提出了一种新型自对准石墨烯场效应晶体管(graphere field-effect transistor,GFET)制备工艺,该工艺可与现有Si CMOS工艺相兼容。利用该工艺制备的自对准栅GFET器件可以消除传统GFET器件制备过程中存在的栅极与漏极和源极覆盖区的寄生电容或栅极与源极和漏极暴露区的寄生电阻,使器件直流特性得到了很大改善。对制作的样品进行直流I-V特性测试时,清楚地观测到了双极型导电特性。制作的沟道长度为1μm的自对准GFET器件样品最大跨导gm为2.4μS/μm,提取的电子与空穴的本征场效应迁移率μeeff和μheff分别为6 924和7 035 cm2/(V·s),顶栅电压VTG为±30 V时,器件的开关电流比Ion/Ioff约为50,远大于目前已报道的最大GFET开关电流比。

A novel fabrication process for self-aligned graphene field-effect transistors （GFET） was proposed, and this process can be compatible with existing Si CMOS process. Using this process of self- aligned gate can eliminate the parasitic capacitance of gate with the drain and the source in the covered area, or the parasitic resistance of gate with the source and the drain exposed area of traditional GFETs exist in the process, and the device DC characteristics are improved greatly. To make samples for I-V DC characteristics of the tests, the bipolar type conductive properties were observed clearly. The I-V characteristics of GFET samples with channel length of 1 μm give a maximum transconductance gmOf 2.4 μS/μm, the extracted of intrinsic field effect mobility of electrons and holes/xμff and/xμffare 6 924 and 7 035 cm2/ （V · s） , respectively. When the top gate voltage VTG is ＂4＂30 V, the ratio of the on-off current lo,/Ioff of the device is about 50, which is much more than the biggest reported GFET on-off current ratio at present.