分离通路浮点乘加器设计与实现

Design and Implementation of Separated Path Floating-point Fused Multiply-Add Unit

针对传统浮点融合乘加器会增加独立浮点加减法、乘法等运算延迟的缺点,首先设计并实现了一种分离通路浮点乘加器SPFMA,通过分离乘法和加法通路,在保持融合乘加运算延迟6拍延迟不变的情况下,将独立乘法和加法等运算延迟由6拍减为4拍,克服了传统融合乘加器的缺点。然后经专用工艺单元库逻辑综合评估,SPFMA可工作在1.2GHz以上,面积60779.44um2。最后在硬件仿真加速器平台上运行SPEC CPU2000浮点测试课题对其进行性能评估,结果表明所有浮点课题性能均有所提高,最大提高5.25%,平均提高1.61%,证明SPFMA可进一步提高浮点性能。

Considering the shortcoming that the fused multiply-add（FMA）unit increases the latency of separate floa- ting-point addition and multiplication operations, a separated path FMA（SPFMA）unit was designed and implemented firstly. The SPFMA unit can reduce the multiplication and addition latency from 6 cycles to 4 cycles while keeping the FMA operation latency to 6 cycles by separating the multiplication and addition path, overcoming the shortcoming of traditional FMA unit. Then utilizing the specific technology cell library, the SPFMA was logically synthesized and could work at 1.2GHz above with area about 60779.44um2. Finally based on the hardware emulation accelerating platform, the performance of the SPFMA unit was estimated through running the SPEC CPU2000 floating-point benchmarks. It turned out that the performances of the benchmarks are all improved, 5. 25% at most and 1.61% on average, which proves that the SPFMA unit helps to promote floating-point performance further.