FDAADS系统中模拟CMOS单元电路的自动综合

Automatic Synthesis of Cell level CMOS Analog Circuits in FDAADS

介绍了一种基于优化的 CMOS单元电路的自动综合方法 ,该方法利用一种新颖的电路性能评估技术来缩短综合软件的运行时间、提高设计精度 .此外 ,采用模拟退火法优化算法进行求解 ,并结合一些其它方法来提高获得全局优化解的能力 .利用上述方法实现的一些 CMOS单元电路的自动综合模块已经集成到 FDAADS——“复旦模拟电路自动化设计系统”中 .大量的实验结果表明

A optimization based approach for automatic synthesis of cell level CMOS analog circuits is presented.In order to shorten run time and promote design accuracy,a novel estimation technique is used to estimate circuit performance.Besides, simulated annealing algorithm and some other measures are taken to assure global optimum results.Synthesis tools for several cell level CMOS analog circuits implemented with the above approach have been integrated in FDAADS—FuDan Analog Circuit Automated Design System.It has been demonstrated that this approach can give accurate design results with a reasonably short run time.