期刊文献+

星载SRAM型FPGA可靠性快速评估技术 被引量:1

Fast reliability evaluation for SRAM-based spaceborne FPGAs
下载PDF
导出
摘要 空间辐射环境严重影响星载SRAM(Static Random Access Memory)型FPGA(Field Programmable Gate Array)的可靠性,提出了星载SRAM型FPGA可靠性快速验证评估方法.在传统故障注入验证的基础上,引入可靠性预评估技术,在逻辑门级分析单粒子翻转对FPGA配置信息位的影响,同时对TMR(Triple Modular Redundancy)冗余方式进行单粒子翻转关键位置评估.然后构成不同敏感级别的故障序列,最后根据应用需求选择不同故障序列进行故障注入从而有效快速评估系统可靠性.该方法与逐位翻转相比,能够在保证故障覆盖率的同时,有效地减少实验时间,提高实验效率. Static random access memory( SRAM)-based field programmable gate arrays (FPGAs) relia- bility is seriously affected by space radiation. A new method for fast reliability evaluation of SRAM-based FP- GAs was proposed. Based on traditional fault injection technique, a pre-evaluation was introduced to analyze the effect of single event upsets (SEU) in logic gate-level and SEU sensitive bits in triple modular redundancy (TMR). Then, the fault sequences of different sensitive level were formed. Finally, different fault sequences were selected depending on the application needs and injected into system for evaluating reliability. The meth- od can not only reduce the experiment times and improve the experiment efficiency but also ensure the fault coverage.
出处 《北京航空航天大学学报》 EI CAS CSCD 北大核心 2013年第7期863-868,共6页 Journal of Beijing University of Aeronautics and Astronautics
关键词 星载FPGA 故障注入 单粒子翻转 可靠性评估 spaceborne FPGA fault injection single event upset reliability evaluation
  • 相关文献

参考文献16

  • 1Kastensmidt F L, Neuberger G, Hentschke R F, et al. Designing fault-tolerant techniques for SRAM-Based FPGAs[ J ]. IEEE De- sign and Test of Computers ,2004,21 ( 6 ) :552-562.
  • 2Sterpone L, Battezzati N. A novel design flow for the performance optimization of fault tolerant circuits on SRAM-based FPGA's [ C]//Keymeulen D. Proceedings of NASA/ESA Conference on Adaptive Hardware and Systems. Los Alamitos: IEEE Computer Society,2008 : 157-163.
  • 3费尔南达·利马·卡斯腾斯密得,路易吉·卡罗,里卡多·赖斯.基于SRAM的FPGA容错技术[M].杨孟飞,龚健,文亮,等译.北京:中国宇航出版社,2009:1-8.
  • 4Manuzzato A, Gerardin S, Paccagnella A, et al. Effectiveness of TMR-based techniques to mitigate alpha-induced SEU accumula- tion in commercial SRAM-based FPGAs [ J ]. IEEE Transactions on Nuclear Science, 2008,55 ( 4 ) : 1968-1973.
  • 5Alderighi M, D'Angelo S, Mancini M, et al. A fault injection tool for SRAM-based FPGAs[ C]//Metra C. Proceedings of IEEE In- ternational On-Line Testing Symposium. Los Alamitos: IEEE Computer Society,2003 : 129-133.
  • 6Alderighi M, Casini F, D'Angelo S, et al. A tool for injecting SEU-like faults into the configuration control mechanism of Xil- inx virtex FPGAs[ C ]//Martin D C. Proceeding of IEEE Interna- tional Symposium on Defect and Fault Tolerance in VLSI Sys- tem. Los Alamitos : IEEE Computer Society,2003:71-78.
  • 7Clark J A,Pradhan D K. Fault injection:a method for validating computer system dependability [ J ]. IEEE Computer, 1995, 28(6) :47-55.
  • 8宋凝芳,秦姣梅,潘雄,江云天.SRAM型FPGA单粒子效应逐位翻转故障注入方法[J].北京航空航天大学学报,2012,38(10):1285-1289. 被引量:14
  • 9Maheshwari A, Koren I, Burleson W. Techniques for transient fault sensitivity analysis and reduction in VLSI circuits [ C ]// Martin D C. Proceedings of the IEEE International Symposium on Defect and Fault-tolerance. Los Alamitos :IEEE Computer So- ciety, 2003 : 597- 604.
  • 10Baraza J C ,Gracia J,Gil D ,et al. Improvement of fault injection techniques based on VHDL code modification [ C ]//Harris I G. IEEE International High-Level Design Validation and Test Workshop. Los Alamitos : IEEE Computer Society, 2005 : 19-26.

二级参考文献8

  • 1费尔南达·利马·卡斯腾斯密得,路易吉·卡罗,里卡多·赖斯.基于SRAM的FPGA容错技术[M].杨孟飞,龚健,文亮,等译.北京:中国宇航出版社,2009:1-8.
  • 2齐鑫,冯文全.基于动态重配置的SEU故障检测与修复系统的设计[C]//方滨兴.中国通信学会第六届学术年会论文集.广州:中国通信学会,2009:82-87.
  • 3Leveugle R, Antoni L, Feher B. Dependability analysis : a new application for run-time reconfiguration [ C ]//Amaral J N. Proceedings of the International Parallel and Distributed Processing Symposium (IPDPS). Los Alamitos: IEEE Computer Society Press, 2003:345 - 351.
  • 4Johnson E,Caffrey M P,Graham P S,et al. Accelerator validation of an FPGA SEU simulator [ J ]. IEEE Transactions on Nuclear Science,2003,50 (6) :2147 - 2157.
  • 5Morgan K S,McMurtrey D L,Pratt B H,et al. A comparison of TMR with alternative fault-tolerant design techniques for FPGAs [ J ]. IEEE Transactions on Nuclear Science, 2007,54 ( 6 ) : 2065 - 2072.
  • 6Quinn H M,Graham P S,Morgan K S,et al. An introduction to radiation-induced failure modes and related mitigation methods for Xilinx SRAM FPGAs [ C ]//Plaks T P. Proceedings of the International Conference on Engeering of Reconfigurable Systems Algorithms( ERSA ). Las Vegas : CSREA Press ,2008 : 139 - 145.
  • 7Yui C, Swift C, Carmichael C. Singel event upset susceptibility testing of the Xilinx Virtex Ⅱ FPGA [ C ]//Katz R B. Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD). Washington D C: Kossiakoff Conference Center,2002:212 - 217.
  • 8Quinn H M, Graham P S, Wirthlin M J, et al. A test methodology for determining space readiness of Xilinx SRAM-Based FPGA devices and designs [J]. IEEE Transactions on Instrumentation and Measurement,2009,58 (10) :3380 - 3395.

共引文献14

同被引文献15

引证文献1

二级引证文献7

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部