摘要
针对当前条件下多核处理器遇到的通信瓶颈问题,设计了一种采用数据驱动机制的片内多核通信结构,该结构包括数据驱动模块和片上路由器.数据驱动模块用来进行数据完备性检测;片上路由器则实现处理器核间的通信及"簇"间通信.在Altera公司的CycloneIII开发板上使用NIOS软核构建了多核系统进行了验证.实验结果表明,本设计可以有效的实现多核片内通信,具有很好的可扩展性.
For the bottleneck of multi--core communication in current technology, this paper presents a multi--core communication based on data driverL This architecture consists of Data Driven Module (DDM) and On- chip Router. DDM checks the data completeness of a procedure while On--chip Router provides communication between processor cores or "clusters". This architecture has been verified using the multi--core system constructed with the NIOS of Altera' s CycionelII. The experiment results show that this architecture can make the communication efficiently and has a good scalability.
出处
《微电子学与计算机》
CSCD
北大核心
2013年第9期58-61,共4页
Microelectronics & Computer
关键词
数据驱动
片上路由器
多核通信
data--driven
on--chip router
multi--core communication