基于FPGA的数字接收系统设计

Design of Digital Receiving System Based on FPGA

高速信号处理的发展对数据采集系统的采样速率和精度提出了越来越高的要求,但受ADC器件的限制,目前单片ADC很难同时做到高采样速率和高精度。本文在对并行交替采集与处理技术研究的基础上,设计了一种基于FPGA并行交替采集与处理的数字接收系统,并通过该系统进行了通道失配误差的测量与校正研究。在FPGA内部完成了通道失配误差测量与校正的实验与仿真,结果验证了通道失配误差测量与校正方法的有效性。

With the development of high-speed signal processing, the data acquisition system needs work at higher sam- piing rate and precision. It is difficult for single ADC to acquire the high sampling rate and precision according to the limit of ADC chip＇s manufacturing. The parallel interleaved acquisition and processing system is designed through the study of parallel interleaved acquisition and processing technology. The channel mismatch error measurement and correc- tion are studied. The channel mismatch error measurement and correction are realized and simulated on FPGA. The re- suits show that the method of the channel mismatch error measurement and correction is effective.