底层相关的VLSI高层次设计策略

Low Level Dependent Design Methodology for High Level VLSI Design

在 VL SI系统设计、行为设计和逻辑设计过程中 ,未考虑到的与半导体制造工艺有关的因素 (如延迟、功耗问题等 )严重影响设计结果的性能 ,以至使物理设计结果的性能远离原来的设计目标 .针对这个问题 ,文中提出与底层有关的 VL SI高层次设计策略 ,将影响性能的底层参数和信息引入高层次设计中 。

In the area of VLSI design automation, since semi conductor technology has progressed to deep sub micron, the factors (such as delay, power consume), that can not be considered in the design phases of high level design, will affect the performance of the design result greatly, and it might cause the performance of physical design result being far from the design aim. For this problem, a low level dependent design methodology for high level VLSI design is proposed. In this approach, the parameters and information in lower level which affect the performance are led to the higher level design process so as to make the physical implementation of the higher level design surely satisfy the request of performance.