可综合RTL级电路模型

Synthesizable Circuit Model in RTL

高层次设计方法使电路的设计发生了巨大的变化,但许多设计者在使用时却感到从语言模型到电路模型的差异使得他们很难掌握这种方法,电路设计后仿真通过率低.文章结合VHDL语言探讨了高层次设计方法在具体设计中的应用,通过明确各种电路的描述方法,提高电路描述的正确性,从而能最大限度地发挥高层设计方法的优点.

High level design methodology make great changes to the circuit design,but many designer feel it difficult to master this method because of the great difference between the language and circuit.The circuit they designed can hardly work properly.This paper discusses the practical use of this method combined VHDL.It can improve the quantity of circuit by defining the commonly used module and can take full advantage of this method．