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基于SIMD处理器的全定制多粒度矩阵寄存器文件 被引量:1

A customized multi-grain matrix register file for SIMD processors
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摘要 在SIMD处理器上映射矩阵运算时会带来大量的数据重排操作从而降低系统性能。本文提出定制化的多粒度矩阵寄存器文件(MMRF)以消除数据重排操作。MMRF支持多粒度的并行行访问和列访问,从而提升矩阵运算的性能。MMRF可以被动态配置为不同的并行访问模式,在不同模式下一个或多个子矩阵可以被并行处理。实验结果显示,同传统的向量寄存器文件(VRF)和矩阵寄存器文件(MRF)相比,MMRF可分别带来2.21倍和1.6倍的平均性能提升,面积分别增加14.3%和3.7%,功耗分别增加14.6%和2.2%。同TMS320C64x+处理器相比,基于SIMD技术的FT-Matrix处理器在引入MMRF后可以得到5.65倍到7.71倍的性能提升。通过层次化的全定制设计技术,MMRF的面积和关键路径分别减少17.9%和39.1%。 Mapping matrix operations on SIMD processors brings a large amount of data rearrangement that lowers the system performance. In this study, a customized Multi-Grain Matrix Register File (MMRF), which supports muhi-gTained parallel row -wise and column-wise access, was proposed to eliminate these data rearrangement and increase the performance of matrix operations. The MMRF could be configured into different parallel access modes, in which one or severel sub-matrices can be accessed in parallel. Experimental results show that, compared with the traditional Vector Register File (VRF) and the MRF, the MMRF can respectively achieve about 2. 21x and 1. 6x average performance improvement, where the area of MMRF increases by 14.3% and 3.7% respectively, and the power of MMRF increases by 14.6% and 2.2% respectively. Compared with TMS320C64x +, the SIMD processor of FT-Matrix can achieve about 5.65x to 7.71x performance improvement by employing the MMRF. By hierarchical customized design technalogy, the area and critical-path delay of MMRF can be reduced by 17.9% and 39. 1% respectively.
出处 《国防科技大学学报》 EI CAS CSCD 北大核心 2013年第4期156-160,共5页 Journal of National University of Defense Technology
基金 国家自然科学基金资助项目(60906014 61070036) 高性能计算联合博导组科研基金项目
关键词 SIMD 矩阵运算 多粒度 矩阵寄存器文件 SIMD matrix operation multi-grain matrix register file
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  • 1Samsung. Downlink MIMO for EUTRA. 3GPP TSG RAN WG1 meeting #44[ R]. 3GPP RI-060335,2006.
  • 2Andrews J, Ghesh A, Muhamed R. Fundamentals of WiMAX : understanding broadband wireless networking [ R ]. Prentice Hall, Mar, 2007.
  • 3Woh M, Seo S, Mahlke S, et al. AnySP: Anytime anywhere anyway signal processing[ C ]. ISCA' 09, June,2009.
  • 4Corbal J, Espasa R, Valero M. MOM: A matrix SIMD instruction set architecture for multimedia applications [ C ]// Proceedings of the ACM/IEEE SC99 Conference, 1999:1 -12.
  • 5Shahbahrami A, Juurlink B, Vassiliadis S. Versatility of extended subwords and the matrix register file [ J ]. ACM Tramactiom on Architecua~ and Code Optimization, 2008,5(1).
  • 6Ciobanu C, Ktuananov G, Gaydedjiev G, et al. A polyraorphie register file for matrix operations[ C]. International Conference Embedded Systems: Architectures, Modeling and Simulation, July, 2006.
  • 7Lin Y, et al. SODA: A low-power architecture for software radio[C]//Proc. of the 33rd Annual International Symposium on Computer Architecture, 2006:89 - 101.
  • 8Flachs B, Asano S, Dhong S H, et al. The microarehitecture of the synergistic processor for a cell processor [ J ]. IEEE Journal of Solid-State Circuits, 2006,41 ( 1 ).
  • 9Krashinsky R, et al. The vector-thread architecture [ C ]// Proceedings of the 31st Annual International Symposium on Computer Architecture, 2004:52 - 63.
  • 10Texas Insmmmfes Incorporated. TMS320C64x + DSP Megamodule Reference Guide[R]. SPRU871J, 2008.

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