基于三维芯片热驱动的扫描测试策略

Three Dimensional ICs Thermal-Driven Test Application Scheme

本文针对三维芯片测试,首先提出了一种扫描结构,这种结构考虑了硅通孔(through silicon vias)互连的代价,在有效的降低测试时间的同时,还可以压缩测试激励数据和测试响应;另外在降低温度方面,扫描树结构也有很好的表现.在三维芯片中的热点(hotspot)经常会影响性能和可靠性.接着,本文提出了一种测试向量排序策略,从而避免测试向量可能会导致温度分布不均,有效的降低了三维芯片的温度.实验结果表明,本文提出的扫描树结构要比传统的扫描链结构在峰值温度方面降低了15%.如果在扫描树结构上应用测试排序策略,芯片上峰值温度可以降低超过25%.

In order to continue the Moore＇s law,three dimensional integrated circuit（3D IC）provides an efficient solution. Although 3D IC has a lot of advantages,it faces a set of challenges.Thermal dissipation is one of the most serious problems.In this paper,we proposed a scan architecture for 3D IC testing.Moreover,we develop a test ordering scheme in order to prevent hotspot in the 3D IC from getting higher.Experiment results present that the peak temperature can be reduced by 15%.When combined with test ordering scheme,the three dimensional scan tree can even reduce peak temperature by more than 25%.