摘要
介绍一种采用FPGA计算2 048点10 bit块浮点的FFT(Fast Fourier Transform)的硬件实现方法。采用递归结构实现FFT处理模块,硬件资源消耗少;采用块浮点算法实现蝶形运算中的乘加运算,有很好的速度和精度;根据旋转因子特性减少50%的ROM资源。同时,本算法在高频带内幅值和频率检测更加精确。
This paper introduces a method of hardware implementation working out 2048-point 10bit block floating- point FFT with FPGA. The design uses the recursive structure to realize FFT processor, reducing the hardware resources. The application of blocking floating-point implement multiplication addition operation in butterfly module guarantees high-speed and accuracy. The characteristics of twiddle factor reduce 50 percent of the ROM resources. Meanwhile, the design has higher accuracy in detection of amplitude and frequency.
出处
《电子器件》
CAS
北大核心
2013年第4期506-509,共4页
Chinese Journal of Electron Devices
基金
国家质检公益性行业科研专项经费项目(编201110233)
江苏高校优势学科建设工程资助项目
关键词
块浮点
递归结构
资源消耗
高频
block floating-point
recursive structure
resource consumption
high frequency
