期刊文献+

轨道交通安全平台主控制单元同步机制研究 被引量:2

Research on MPU synchronization mechanism of urban rail transit vehicle operation and control system
下载PDF
导出
摘要 城市轨道交通车载运控系统是信号系统整体架构中保证列车运行安全,实现行车指挥和列车运行现代化,提高运输效率的关键系统设备;而其主控制单元(MPU)作为控制该系统内多个子系统的核心部件,需通过引入多重硬件冗余技术以确保系统的可靠性及安全性,因此在其硬件设计过程中需要引入可实现各冗余模块在时间上严格协同工作的同步机制。基于上述背景,提出一种应用于轨道交通车载运控系统MPU的硬件同步机制,可实现三模块冗余硬件设计架构下各判决模块间时间同步,并通过对该方法实现过程的讨论及其硬件兼容性等问题的分析,并测试了该方法的实际效果。 Urban rail transit vehicle operation and control system is a key system equipment to realize the modernization of traffic control and train operation,and improve transport efficiency.Its main processing unit(MPU),which is the core unit of the multiple subsystems of the control system,need to introduce multiple hardware redundancy in order to ensure the system reliability and security,so the synchronization mechanism should be introduced to ensure the collaborative work of all redundant modules in the hardware design process.Based on the above background,this paper presents a hardware synchronization mechanism used in rail transit vehicle operation and control system main processing unit(MPU),which can achieve the time synchronization of all the three redundant modules.Furthermore,the effectiveness of this mechanism is also verified by analyzing the design architecture,and tests the practical effect of this method.
出处 《电子测量技术》 2013年第8期93-98,共6页 Electronic Measurement Technology
基金 上海市科委科研计划(10511500306)项目资助
关键词 轨道交通 安全计算机 车载主控制单元 三取二结构 硬件同步 FPGA rail transit vital computer on-board operation and control system 2out of 3structure hardware synchronization field programmable gate array
  • 相关文献

参考文献10

二级参考文献47

共引文献77

同被引文献21

  • 1OSTLER P S, CAFFREY M P, GIBELYOU D S, et al.SRAM FPGA reliability analysis for harsh radiation en- vironments[ J]. IEEE Transactions on Nuclear Science, 2009, 56(6): 3519-3526.
  • 2YIN P Y, CHE Y H. A multi-stage fault-tolerance multiplier with Triple Module Redundancy (TMR) technique[ C]. 2013 4th International Conference on Intelligent Systems Modelling & Simulation (ISMS) , Bangkok, Thailand, 2013:636-641.
  • 3PRATY B, CAFFREY M, CARROLL J F, et al. Fine- grain SEU mitigation for FPGAs using TMR [ J ]. IEEE Transactions on Nuclear Science ,2008,55 (4) :2274-2280.
  • 4ZIPF P. Applying dynamic reconfiguration for fault tol- erance in fine-grained logic arrays [ J ]. IEEE Transac-tion on Very Large Scale Integration (VLSI) Systems , 2008, 16(2) : 134-143.
  • 5MOHAMMAD S, GABRIEL D, TYRRELL A M, et al. Novel bio-inspired approach for fault-tolerant VI_SL sys- tems [J]. IEEE Transaction on Very Large Scale Inte- gration(VLSI) Systems, 2013, 21(10) : 1878-1891.
  • 6DUTT S, VERMA V, SUTHAR V. Built-in-test of FP- GAs with provable ingnosabilities and high diagnostics coverage with application to online testing [ J]. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems,2008, 27 (6) : 309-326.
  • 7石鑫,李昊.无线MIMO-OFDM通信系统原理及其关键技术[J].国外电子测量技术,2010,29(2):32-35. 被引量:16
  • 8郝国锋,王友仁,张砦,孙川.可重构硬件内建自测试与容错机制研究[J].仪器仪表学报,2011,32(4):856-862. 被引量:20
  • 9郝国锋,王友仁,张砦,袁鹏,孔德明.可重构硬件芯片级故障定位与自主修复方法[J].电子学报,2012,40(2):384-388. 被引量:26
  • 10王南天,钱彦岭,李岳,卓清琪,李廷鹏.胚胎型在线自修复FIR滤波器研究[J].仪器仪表学报,2012,33(6):1385-1391. 被引量:12

引证文献2

二级引证文献6

相关作者

内容加载中请稍等...

相关机构

内容加载中请稍等...

相关主题

内容加载中请稍等...

浏览历史

内容加载中请稍等...
;
使用帮助 返回顶部