LTE中灵活并行无冲突Turbo码交织器的实现

A Flexible Parallel Non-conflict Interleaver for LTE Turbo Decoder

为了满足LTE标准中Turbo译码器并行高速的译码要求,设计了一种支持并行译码、存储器访问无冲突的交织器结构.通过对交织器计算公式的推导简化,降低了交织器地址计算的复杂度,同时减少了地址计算单元,只需要一个块地址计算单元即可得到所有存储器的块地址值以及置换网络的控制值.该交织器结构能够实时计算交织地址值,同时灵活性非常高,能够支持多种并行度切换的Turbo译码器.设计的结构在SMIC0.13μm工艺下完成综合,面积为0.023mm2,等效门数为4.5k,最高时钟频率为315MHz.

An architecture supporting non-conflict memory access in parallel high speed turbo decoding is proposed to meet the requirement of LTE.The proposed method reduces the address calculation complexity by simplifying the formula for calculation of the QPP interleaver.And it only needs one address calculation unit to get all of the memory addresses and control bits needed by the permutation network.The structure can calculate the address in real time and support the switching of the control signals of the network for Turbo decoders with different parallelism.The design is synthesized with SMIC 0.13 μ m technology with an area of 0.023mm 2 and equivalent gates of 4.5k.The maximum clock frequency of 315MHz is achieved under SS corner.