先进逻辑工艺下SRAM漏电流测试

Measurement of SRAM Standby Leakage under Advanced Logic Process

对于65nm及以下的先进逻辑工艺,SRAM的漏电流功耗占据了保持状态下功耗的一半以上,成为降低功耗的主要瓶颈之一.精确测量漏电流成为优化工艺从而降低功耗的先决条件.在保持SRAM原有版图环境不变的情况下,通过对SRAM施加不同激励,将栅漏电流、结漏电流和衬底漏电流这3种漏电流有效地区分出来.通过大量的测试,得到在不同温度下SRAM漏电流的相应数据结果用以分析,并对漏电流在整片晶圆内的系统波动和局部随机波动进行了讨论.

For 65 nm and beyond technology, SRAM design cares lower-power application more than ever. Since SRAM leakage consumes over half of total leakage power in standby mode, it＇s top priority to measure SRAM leakage current precisely for further leakage reduction technologies. A novel method for SRAM cell standby leakage measurement is proposed, which enables accurate testing and decoupling of substrate, gate and junction leakage currents in each SRAM cell transistor without any change of the front-end SRAM array layout to preserve actual physical environment. The corresponding test data under different temperatures for analysis is obtained via wafer mapping test. The systematic variation and local random variation of SRAM leakage current on whole wafer are also discussed.