一种高吞吐率CABAC硬件编码器设计

Design on High Throughput CABAC Hardware Encoder

基于1 bin/周期吞吐率CABAC硬件编码器结构,采取旁路编码bin(BB)编码加速设计可进一步提升CABAC编码性能。通过功能合理划分的ARR、ARL两级流水线结构,并有效控制电路关键路径长度,实现了单周期N-BB编码、单周期1RB+1BB两种BB编码加速技术。在相同时钟频率条件下将CABAC编码器BB编码周期数降低到参考设计的2%,并使CABAC编码器的流水线吞吐率提升18%,达到1.18 bin/周期,编码器绝对吞吐率实现682 Mbin/s,而电路面积相对于原编码器仅增加4%。

Based on the 1 bin/cycle throughput CABAC hardware encoder architecture of previous work, CABAC encoding performance can be further improved by accelerating bypass bin （BB） coding. With proper coding function participation, a two - stage pipeline architecture was designed to accelerate BB coding. Two acceleration mechanisms were implemented,including N - BB/cyele coding and 1RB （regular bin） ＋ 1BB/eycle coding. The BB encoding cycles has been reduced to 2% of that of the reference CABAC encoder design at the same clock frequency, and the encoding pipeline throughput has been enhanced by 18%. 1.18 bin/cycle pipeline throughput and 682M bin/s CABAC encoder absolute throughput were achieved, while the circuit area of the proposed design increased only by 4%.