摘要
A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.
A 14-bit 250-MS/s current-steering digital-to-analog converter（DAC） was fabricated in a 0.13μm CMOS process.In conventional high-speed current-steering DACs,the spurious-free dynamic range（SFDR） is limited by nonlinear distortions in the code-dependent switching glitches.In this paper,the bottleneck is mitigated by the time-relaxed interleaving digital-random-return-to-zero（TRI-DRRZ）.Under 250-MS/s sampling rate,the measured SFDR is 86.2 dB at 5.5-MHz signal frequency and 77.8 dB up to 122 MHz.The DAC occupies an active area of 1.58 mm2 and consumes 226 mW from a mixed power supply of 1.2/2.5 V.
基金
supported by the National High Technology Research and Development Program of China(No.SS2013AA011203)
the Specialized Research Fund for the Doctoral Program of Higher Education of China(No.20110002110058)
