AES密码算法的FPGA实现与仿真

Implementation and Simulation of AES Encryption Algorithm based on FPGA

通过对高级加密标准AES算法进行描述,给出了基于FPGA设计的具体设计流程和方法。采用多轮加密过程共用一个轮运算的顺序结构。由于文中的加密模块与解密模块采用相关且不同的初始密钥和不同的密钥扩展模块,结果加强了通信的安全性。采用16位并行总线数据结构,利用16位输入128输出的FIFO数据缓存器对输入数据进行缓存,从而完成数据的加解密。最后通过ISE 13.1仿真验证了该算法设计的正确性。

AES （Advanced encryption standard） is and method is given. The AES Algorithm is designed analyzed, and the specific design process in sequential architecture. As both the encryption module and decryption module use relevant and different initial key and key expansion module, the security of the communication could be strengthened. The 16-bit parallel bus communication interface is used, and the input and 128 output of FIFO data buffer is also employed to cache input data and finish the data encryption. The correctness of algorithm design is verified by ISE 13.1 simulation software.